使用子模块实现三输入数的大小比较
小于 1 分钟
使用子模块实现三输入数的大小比较
`timescale 1ns/1ns
module main_mod(
input clk,
input rst_n,
input [7:0]a,
input [7:0]b,
input [7:0]c,
output [7:0]d
);
wire [7:0] m,n;
sub_mod mod_ab(
.clk(clk),
.rst_n(rst_n),
.data_a(a),
.data_b(b),
.data_c(m)
);
sub_mod mod_am(
.clk(clk),
.rst_n(rst_n),
.data_a(a),
.data_b(c),
.data_c(n)
);
sub_mod mod_mn(
.clk(clk),
.rst_n(rst_n),
.data_a(m),
.data_b(n),
.data_c(d)
);
endmodule
module sub_mod(
input clk,
input rst_n,
input [7:0] data_a,
input [7:0] data_b,
output reg [7:0] data_c
);
always @(posedge clk or negedge rst_n)
if(!rst_n)
data_c <= 0;
else if(data_a > data_b)
data_c <= data_b;
else
data_c <= data_a;
endmodule
module compare_tb;
reg rst_n = 0;
reg clk = 0;
reg [7:0] a = 0;
reg [7:0] b = 0;
reg [7:0] c = 0;
initial begin
rst_n = 0; #100;
rst_n = 1; #300;
a = 8'd3; #0;
b = 8'd5; #0;
c = 8'd7; #0;
#10000;
$finish;
end
always begin #5 clk = !clk; end
main_mod compare_test(
.clk(clk),
.rst_n(rst_n),
.a(a),
.b(b),
.c(c)
);
initial
begin
$dumpfile("compare_test.vcd");
$dumpvars(0, compare_test);
end
endmodule
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